1. Field of the Invention
This invention relates to binary digital logic inverter gates and particularly to extremely high speed logic inverter gates which may be fabricated as arrays of 500 or more gates on a single integrated circuit chip.
2. Description of the Prior Art
Present day digital logic circuits are manufactured from logic modules which are selected to perform a desired logic function and then connected to other logic modules to form a desired logic circuit. A logic module typically includes an external package having a plurality of sturdy external leads that may be connected to a printed circuit board or other type of conductor for communication with the external leads of a similar logic module. Secured within the external package of the logic module is a semiconductor chip containing the transistors, diodes and other circuit components that are required to perform the logic functions of the logic module. Tiny wires connect terminal pads on the semiconductor chip with the external leads of the logic module to permit electrical communication between the logic chips of different logic modules. The logic circuitry of each semiconductor chip is in turn formed from standard logic blocks or gates of which the inverter gate is usually the basic logical building block. In some types of digital logic circuitry, inverter gates are selectively combined to form NAND gates, NOR gates or more complex standard logic gates, while in others a single inverter gate may be modified to form one or more of these gates. Such circuits typically provide relatively large voltage swings between different logic levels to provide good noise immunity for interchip communication. However, because inherent chip capacitances must charge through these large voltage swings, relatively large time delays of several nanoseconds or relatively large currents are consumed by the gate circuits. As logic functions have become more and more complex, they have been constructed by placing more and more standard logic circuits on each semiconductor chip. This technique fails to recognize the fact that only logic gates that are in communication with other chips need a high noise immunity. Very little noise is encountered by circuitry that is connected solely within a single chip. Voltage swings below 0.5 volt and of 0.133 volt or less become possible where only intrachip circuit connections are encountered.